1. Field of the Invention
The present invention relates to a television tuner using an integrated circuit.
2. Description of the Related Art
A conventional television tuner will be described with reference to FIG. 5. An integrated circuit 10 has two sides opposite to each other, and each side has twelve terminals (each number inside circles representing terminals indicates a terminal number in the figure).
Terminal Nos. 1 to 12 are provided on one side 10a, and terminal Nos. 13 to 24 are provided on the other side 10b. Further, as schematically illustrated in the figure, a plurality of circuits is provided inside the integrated circuit, and the respective circuits are connected to the terminals provided on both sides 10a and 10b. In the respective circuits, balanced-input terminals of a UHF mixing circuit 11 are connected to the terminal Nos. 23 and 24, and a non-balanced input terminal of a VHF mixing circuit 12 is connected to the terminal No. 22. Further, balanced-output terminals of the UHF mixing circuit 11 and the VHF mixing circuit 12 are connected to the terminal Nos. 19 and 20, respectively.
Local oscillating signals are supplied from two oscillating circuits, that is, a VHF low-band oscillating circuit (hereinafter, referred to as a low-band oscillating circuit) 13 and a VHF high-band oscillating circuit (hereinafter, referred to as a high-band oscillating circuit) 14 to the VHF mixing circuit 12. The low-band oscillating circuit 13 is a non-balanced type circuit, and a resonance circuit coupling terminal thereof is connected to the terminal No. 1. Further, the high-band oscillating circuit 14 is a balanced type circuit, and two resonance circuit coupling terminals thereof are connected to the terminal Nos. 2 and 3, respectively. Local oscillating signals from a UHF oscillating circuit 15 are supplied to the UHF mixing circuit 11. The UHF oscillating circuit 15 is also a balanced type circuit, and two resonance circuit coupling terminals thereof are connected to the terminal Nos. 4 and 5, respectively.
Channel selection data is input from a television receiver body (not shown) to the terminal Nos. 14 to 16. More specifically, frequency data for channel selection or band switching data (referred to as channel selection data) is input to the terminal No. 14, and a clock signal is input to the terminal No. 15. In addition, a voltage for identifying an address (address identifying voltage) is applied to the terminal No. 16. These clock signal and channel selection data are input to a PLL circuit 17 and a switching voltage generating circuit 18 through an interface 16.
The address identifying voltage allows only the channel selection data among various types of data output from the television receiver body to be input to the integrated circuit 10. The address identifying voltage is set corresponding to 2-bit address data included in the channel selection data. For example, when the address data is specified as (1, 0), the address identifying voltage is set in the range of from 2V to 3V. This voltage is set by diving a source voltage of 5V by a voltage dividing resistor (not shown) provided at the outside of the integrated circuit, and the divided voltage is applied to the terminal No. 16.
An address identifying circuit (not shown) to which the address identifying voltage is input is provided in the interface 16. The address identifying circuit sets the interface to receive only the channel selection data.
Frequency data and local oscillating signals output from the respective oscillating circuits 13, 14, and 15 are input to the PLL circuit 17. An error signal output from the PLL circuit 17 is DC converted by a charge pump 20 having a low-pass filter. Then, a tuning voltage is output from a tuning voltage generating circuit 21 to the terminal No. 10.
Further, band switching data is input to the switching voltage generating circuit 18, and a band switching voltage is output to the terminal Nos. 17 and 18.
Peripheral circuits provided at the outside of the integrated circuit are connected to the integrated circuit 10. A first resonance circuit 28 is utilized when receiving a low-band signal in a VHF band. One terminal thereof is coupled to the terminal No. 1, and the other terminal thereof is connected to the ground. Further, a second resonance circuit 29 is utilized when receiving a high-band signal in the VHF band. One terminal thereof is connected to the terminal No. 2, and the other terminal thereof is connected to the terminal No. 3. Furthermore, a third resonance circuit 30 is utilized when receiving a UHF band signal. One terminal thereof is connected to the terminal No. 4, and the other terminal is connected to the terminal No. 5. Varactor diodes (not shown) for changing a resonance frequency are provided in the respective resonance circuits 28, 29, and 30. The tuning voltage output from the terminal No. 10 is applied to the respective varactor diodes, (for example, see Japanese Unexamined Patent Application Publication No. 2003-234971 (FIG. 1)).
Further, with respect to circuits (circuits provided at the inside and at the outside of the integrated circuit 10) connected to terminals other than the above-mentioned terminals, a description thereof will be omitted.
In the above-mentioned construction, since a dedicated terminal (terminal No. 16) is provided for applying the address identifying voltage generated at the outside of the integrated circuit, the number of terminals increases. Therefore, there is a limitation to reduce the size of the integrated circuit.